A design technique of 50 ? terminated bandpass matching network and its implementation to a Y-shaped monopole antenna matching

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Küçük Resim

Tarih

2016-12

Dergi Başlığı

Dergi ISSN

Cilt Başlığı

Yayıncı

Springer New York LLC

Erişim Hakkı

info:eu-repo/semantics/closedAccess

Özet

In this paper, a 50 ? terminated or in other words transformerless bandpass matching network design methodology and an implementation example are presented. The real frequency techniques are powerful numerical methods to design wideband lossless two-port networks such as filters, matching networks and amplifiers. In these techniques, the value of the termination resistance of the designed network could not be yielded as 50 ? by numerical package. Hence, a transformer is also required for 50 ? termination which is not practical for high frequency applications. By employing the proposed procedure, it is guaranteed to obtain transformerless bandpass matching network. Also in this study a wideband suspended monopole antenna is examined. The proposed antenna consists of two major elements; Y-shaped impedance matching plate and hemi-circular radiator. Moreover Y-shaped impedance matching plate connected to a feeding probe excites the suspended hemi-circular radiator via air gap. Consequently, a transformerless bandpass matching network is designed to filter and expand the operational frequency bandwidth of the proposed antenna. It has been observed that ideal circuit and the layout of the matching network simulation have good agreement.

Açıklama

Anahtar Kelimeler

Bandpass matching network, Real frequency technique, Single matching problem, Suspended monopole antenna, Transformerless design

Kaynak

Analog Integrated Circuits and Signal Processing

WoS Q Değeri

Scopus Q Değeri

Q3

Cilt

89

Sayı

SI
3
SI

Künye

Aydın, Ç., Atilla, D. Ç., Köprü, R., Kılınç, S., Karakuş, C. & Yarman, B. S. B. (2016). A design technique of 50 Ω terminated bandpass matching network and its implementation to a Y-shaped monopole antenna matching.Analog Integrated Circuits and Signal Processing, ,89(3), 665-673. doi:10.1007/s10470-016-0768-3