A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC

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IEEE Computer Soc

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This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 390) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.


Anahtar Kelimeler

Architecture, Area costs, Bit-serial architecture, Bit-serial pipeline architecture, Calculators, Computational complexity, Computer architecture, Copying, Data storage equipment, Diamond search, Efficient, Encoding, Equations, H.264/AVC, H.264/AVC encoder, Hardware resources, High-performance, Image coding, Image resolution, Macroblock processing, Mathematical model, Memory requirement, Memory requirements, Modular, Motion estimation, Motion Picture Experts Group standards, Multimedia devices, Pipeline architectures, Pipelines, Pixel, Pixels, Portable multimedia devices, Power consumption, Power consumptions, Proposed architectures, Reusable architectures, Serial architectures, Signal processing, Subpixel motion estimation, Sub-pixel motion estimation, Video coding, Video compression, VLSI, VLSI architecture, VLSI architectures


2008 Fourth International Conference On Intelligent Information Hiding And Multimedia Signal Processing, Proceedings

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Fatemi, M. R. H., Ateş, H. F. & Salleh, R. (2008). A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC. Paper presented at the 818-821. doi:10.1109/IIH-MSP.2008.280