Realization of processing blocks of CNN based CASA system on CPU and FPGA

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dc.authorid0000-0003-1282-0340
dc.authorid0000-0003-3988-0941
dc.authorid0000-0003-3377-2560
dc.authorid0000-0001-8590-1518
dc.contributor.authorŞavkay, Osman Leventen_US
dc.contributor.authorCesur, Evrenen_US
dc.contributor.authorYıldız, Nerhunen_US
dc.contributor.authorYalçın, Mustak Erhanen_US
dc.contributor.authorTavşanoğlu, Ahmet Vedaten_US
dc.date.accessioned2019-06-27T18:40:37Z
dc.date.available2019-06-27T18:40:37Z
dc.date.issued2014
dc.departmentIşık Üniversitesi, Mühendislik Fakültesi, Elektrik-Elektronik Mühendisliği Bölümüen_US
dc.departmentIşık University, Faculty of Engineering, Department of Electrical-Electronics Engineeringen_US
dc.description.abstractIn this paper, hardware optimization of the preprocessing and software implementation of the processing blocks of a computer aided semen analysis (CASA) system are proposed, which is also implemented on an FPGA and ARM device as a working prototype. The software implementation of the track initialization, track maintenance, data validation and classification blocks of the processing part are implemented on a Zynq7000 ARM Cortex-A9 processor. In the preprocessing part, a real-time cellular neural network (CNN) emulator (RTCNNP-v2) is used for the realization of the image processing algorithms, whose regular, flexible and reconfigurable infrastructure simplifies the prototyping process. The CASA system introduced in this paper is capable of processing full-HD 1080p@60 (1080 x 1920) video images in real-time.en_US
dc.description.versionPublisher's Versionen_US
dc.identifier.citationŞavkay, O. L., Cesur, E., Yıldız, N., Yalçın, M. E. & Tavşanoğlu, A. V. (2014). Realization of processing blocks of CNN based CASA system on CPU and FPGA. Paper presented at the 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2081-2084. doi:10.1109/ISCAS.2014.6865576en_US
dc.identifier.doi10.1109/ISCAS.2014.6865576
dc.identifier.endpage2084
dc.identifier.isbn9781479934324
dc.identifier.isbn9781479934317
dc.identifier.issn0271-4302
dc.identifier.issn2158-1525
dc.identifier.scopus2-s2.0-84907411217
dc.identifier.scopusqualityN/A
dc.identifier.startpage2081
dc.identifier.urihttps://hdl.handle.net/11729/1636
dc.identifier.urihttp://dx.doi.org/10.1109/ISCAS.2014.6865576
dc.identifier.wosWOS:000346488600522
dc.identifier.wosqualityN/A
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.indekslendigikaynakConference Proceedings Citation Index – Science (CPCI-S)en_US
dc.institutionauthorTavşanoğlu, Ahmet Vedaten_US
dc.institutionauthorid0000-0001-8590-1518
dc.language.isoenen_US
dc.peerreviewedYesen_US
dc.publicationstatusPublisheden_US
dc.publisherIEEEen_US
dc.relation.ispartof2014 IEEE International Symposium on Circuits and Systems (ISCAS)en_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectSemen Characteristicsen_US
dc.subjectImage processingen_US
dc.subjectIIR filtersen_US
dc.subjectBandpass filtersen_US
dc.subjectARM processorsen_US
dc.subjectCellular neural networksen_US
dc.subjectComputer aided analysisen_US
dc.subjectImage processingen_US
dc.subjectData validationen_US
dc.subjectHardware optimizationen_US
dc.subjectImage processing algorithmen_US
dc.subjectPrototyping processen_US
dc.subjectReconfigurable infrastructuresen_US
dc.subjectSoftware implementationen_US
dc.subjectTrack initializationen_US
dc.subjectTrack maintenanceen_US
dc.subjectVideo signal processingen_US
dc.titleRealization of processing blocks of CNN based CASA system on CPU and FPGAen_US
dc.typeConference Objecten_US
dspace.entity.typePublication

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