Cryogenic PLL for quantum computing at 130nm by using ring VCO for 5GHz application

With the continuous acceleration of modern wireless communication techniques and processors, the amount of transmitted and processed data has significantly increased, making Phase-Locked Loops (PLLs) more critical than ever. Today, PLLs are integrated as essential building blocks in numerous commercial electronic products and integrated circuits, placing them at the center of a highly competitive research domain. However, the emergence of advanced computational platforms, particularly for quantum technologies, has introduced new operational requirements for PLLs. Among these, cryogenic PLLs designed to operate at extremely low temperatures have gained increasing importance. In this work, a complete schematic based transistor-level cryogenic PLL is designed and simulated using the 130 nm SkyWater CMOS technology in the NGSPICE environment. Conventional MOSFET models are adapted to cryogenic operation to capture the low-temperature device behavior accurately. A threestage pseudo-differential Voltage-Controlled Oscillator (VCO) architecture is implemented, achieving stable oscillation at around 5 GHz with an output amplitude of 1.8V. The results demonstrate the feasibility of reliable highfrequency PLL operation under cryogenic conditions, which is crucial for integration with quantum computing readout and control systems.