Cryogenic PLL for quantum computing at 130nm by using ring VCO for 5GHz application

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dc.authorid0000-0002-6706-7352
dc.contributor.authorYüce, Mirzaen_US
dc.contributor.authorKöprü, Ramazanen_US
dc.date.accessioned2026-03-09T11:37:09Z
dc.date.available2026-03-09T11:37:09Z
dc.date.issued2025-11-29
dc.departmentIşık Üniversitesi, Mühendislik ve Doğa Bilimleri Fakültesi, Elektrik-Elektronik Mühendisliği Bölümüen_US
dc.departmentIşık University, Faculty of Engineering and Natural Sciences, Department of Electrical-Electronics Engineeringen_US
dc.description.abstractWith the continuous acceleration of modern wireless communication techniques and processors, the amount of transmitted and processed data has significantly increased, making Phase-Locked Loops (PLLs) more critical than ever. Today, PLLs are integrated as essential building blocks in numerous commercial electronic products and integrated circuits, placing them at the center of a highly competitive research domain. However, the emergence of advanced computational platforms, particularly for quantum technologies, has introduced new operational requirements for PLLs. Among these, cryogenic PLLs designed to operate at extremely low temperatures have gained increasing importance. In this work, a complete schematic based transistor-level cryogenic PLL is designed and simulated using the 130 nm SkyWater CMOS technology in the NGSPICE environment. Conventional MOSFET models are adapted to cryogenic operation to capture the low-temperature device behavior accurately. A threestage pseudo-differential Voltage-Controlled Oscillator (VCO) architecture is implemented, achieving stable oscillation at around 5 GHz with an output amplitude of 1.8V. The results demonstrate the feasibility of reliable highfrequency PLL operation under cryogenic conditions, which is crucial for integration with quantum computing readout and control systems.en_US
dc.description.versionPublisher's Versionen_US
dc.identifier.citationYüce, M. & Köprü, R. (2025). Cryogenic PLL for quantum computing at 130nm by using ring VCO for 5GHz application. Paper presented at the 2025 16th International Conference on Electrical and Electronics Engineering (ELECO), 1-5. doi:https://doi.org/10.1109/ELECO69582.2025.11329329en_US
dc.identifier.endpage5
dc.identifier.isbn9798331546946
dc.identifier.isbn9798331546953
dc.identifier.startpage1
dc.identifier.urihttps://hdl.handle.net/11729/7109
dc.identifier.urihttps://doi.org/10.1109/ELECO69582.2025.11329329
dc.institutionauthorYüce, Mirzaen_US
dc.institutionauthorKöprü, Ramazanen_US
dc.institutionauthorid0000-0002-6706-7352
dc.language.isoenen_US
dc.peerreviewedYesen_US
dc.publicationstatusPublisheden_US
dc.publisherIEEEen_US
dc.relation.ispartof2025 16th International Conference on Electrical and Electronics Engineering (ELECO)en_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Öğrencien_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.titleCryogenic PLL for quantum computing at 130nm by using ring VCO for 5GHz applicationen_US
dc.typeConference Objecten_US
dspace.entity.typePublicationen_US

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