A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264

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dc.authorid0000-0001-9486-3226
dc.authorid0000-0002-6842-1528
dc.authorid0000-0002-7379-8397
dc.contributor.authorFatemi, Mohammad Reza Hosseinyen_US
dc.contributor.authorAteş, Hasan Fehmien_US
dc.contributor.authorSalleh, Rosli Binen_US
dc.date.accessioned2019-07-30T19:46:06Z
dc.date.available2019-07-30T19:46:06Z
dc.date.issued2009
dc.departmentIşık Üniversitesi, Mühendislik Fakültesi, Elektrik-Elektronik Mühendisliği Bölümüen_US
dc.departmentIşık University, Faculty of Engineering, Department of Electrical-Electronics Engineeringen_US
dc.descriptionM This work was supported in part by the Ministry of Higher Education, Malaysia, under Grant FRGS FP094/2007c.en_US
dc.description.abstractBit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing and etc. These attractive features make them suitable for using in VLSI design and reduce overall production cost. In this paper, we propose the first least significant bit (LSB) bit-serial sum of absolute difference (SAD) hardware accelerator for integer variable block size motion estimation (VBSME) of H.264. This hardware accelerator is based on a previous state-of-art bit-parallel architecture namely propagate partial SAD. In order to reduce area cost and improve throughput, pixel truncation technique is adopted. Due to the bit-serial pipeline architecture and using small processing elements, our architecture works at much higher clock frequency (at least 4 times) and reduces area cost about 32% compared with its bit-parallel counterpart. The proposed hardware accelerator can be used in different disciplines from low bit rate to high bit rate by making a tradeoff between the degree of parallelism or using fast algorithm or a combination of both.en_US
dc.description.sponsorshipMinistry of Education, Malaysiaen_US
dc.description.versionPublisher's Versionen_US
dc.identifier.citationFatemi, M. R. H., Ateş, H. F. & Salleh, R. B. (2009). A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264. Paper presented at the 2009 Innovative Technologies in Intelligent Systems and Industrial Applications, 1-4. doi:10.1109/CITISIA.2009.5224251en_US
dc.identifier.doi10.1109/CITISIA.2009.5224251
dc.identifier.endpage4
dc.identifier.isbn9781424428861
dc.identifier.isbn9781424428878
dc.identifier.scopus2-s2.0-70449103599
dc.identifier.scopusqualityN/A
dc.identifier.startpage1
dc.identifier.urihttps://hdl.handle.net/11729/1667
dc.identifier.urihttp://dx.doi.org/10.1109/CITISIA.2009.5224251
dc.identifier.wosWOS:000277386000001
dc.identifier.wosqualityN/A
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.indekslendigikaynakConference Proceedings Citation Index – Science (CPCI-S)en_US
dc.institutionauthorAteş, Hasan Fehmien_US
dc.institutionauthorid0000-0002-6842-1528
dc.language.isoenen_US
dc.peerreviewedYesen_US
dc.publicationstatusPublisheden_US
dc.publisherIEEEen_US
dc.relation.ispartof2009 Innovative Technologies in Intelligent Systems and Industrial Applicationsen_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectArchitectureen_US
dc.subjectDesignen_US
dc.subjectArea costen_US
dc.subjectBit-parallelen_US
dc.subjectBit-serialen_US
dc.subjectBit-serial architectureen_US
dc.subjectClock frequencyen_US
dc.subjectDegree of parallelismen_US
dc.subjectFast algorithmsen_US
dc.subjectHardware acceleratorsen_US
dc.subjectHigh bit ratesen_US
dc.subjectInteger variablesen_US
dc.subjectLeast significant bitsen_US
dc.subjectLow bit rateen_US
dc.subjectLower densityen_US
dc.subjectPipeline architectureen_US
dc.subjectProcessing elementsen_US
dc.subjectProduction costen_US
dc.subjectSum of absolute differencesen_US
dc.subjectTruncation techniquesen_US
dc.subjectVariable block-size motion estimationen_US
dc.subjectVLSI designen_US
dc.subjectCost reductionen_US
dc.subjectImage codingen_US
dc.subjectIndustrial applicationsen_US
dc.subjectIntelligent systemsen_US
dc.subjectMotion estimationen_US
dc.subjectVector quantizationen_US
dc.subjectPipeline processing systemsen_US
dc.subjectCostsen_US
dc.subjectHardwareen_US
dc.subjectClocksen_US
dc.subjectFrequencyen_US
dc.subjectBit rateen_US
dc.subjectPinsen_US
dc.subjectRoutingen_US
dc.subjectVery large scale integrationen_US
dc.subjectProductionen_US
dc.subjectBlock codesen_US
dc.subjectCode standardsen_US
dc.subjectData compressionen_US
dc.subjectParallel architecturesen_US
dc.subjectVideo codingen_US
dc.subjectVLSIen_US
dc.subjectLeast significant bit-serial architectureen_US
dc.subjectSum-of-absolute difference acceleratoren_US
dc.subjectH.264 standarden_US
dc.subjectBit-parallel architectureen_US
dc.subjectPixel truncation techniqueen_US
dc.titleA bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264en_US
dc.typeConference Objecten_US
dspace.entity.typePublication

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