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2015 - 20162
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İndeks: Science Citation Index Expanded (SCI-EXPANDED) × Konu: Cellular neural networks ×

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  • Küçük Resim
    Yayın
    Decomposition of the nodal conductance matrix of a planar resistive grid and derivation of its eigenvalues and eigenvectors using the kronecker product and sum with application to cnn image filters
    (IEEE, 2016-12) Tavşanoğlu, Ahmet Vedat
    It is shown that an (M× N)-node planar resistive grid can be decomposed into two sub-grids; one made up of M N-node horizontal and the other of N M-node vertical linear resistive grids which corresponds to decomposing its nodal conductance matrix (NCM) into the Kronecker sum of the NCMs of horizontal and vertical linear grids. This enables the analytical expressions of the eigenvalues and eigenvectors of the NCMs of the sub-grids as well as those of the planar resistive grid to be expressed in terms of those of the two linear grids, whose analytical expressions are well known. For a Cellular Neural Network (CNN) Gabor-type filter (GTF) we define generalized nodal conductance matrices (GNCMs) that correspond to the NCMs of the resistive sub-grids, show that each Kronecker decomposition has a counterpart in CNN GTF and prove that each GNCM, its counterpart NCM and the corresponding temporal state matrices are related through unitary diagonal similarity transformations. Consequently, we prove that the eigenvalues of the temporal state matrix of a spatial band-pass CNN GTF are the same as those of its counterpart spatial low-pass CNN image filter, hence their temporal transient behaviors are similar in settling to a forced response.
  • Küçük Resim
    Yayın
    Architecture of a fully pipelined real-time cellular neural network emulatort
    (IEEE-INST Electrical Electronics Engineers Inc, 2015-01) Yıldız, Nerhun; Cesur, Evren; Kayaer, Kamer; Tavşanoğlu, Ahmet Vedat; Alpay, Murathan
    In this paper, architecture of a Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v2) is given and the implementation results are discussed. The proposed architecture has a fully pipelined structure, capable of processing full-HD 1080p@60 (1920 1080 resolution at 60 Hz frame rate, 124.4 MHz visible pixel rate) video streams, which is implemented on both high-end and low-cost FPGA devices, Altera Stratix IV GX 230, and Cyclone III C 25, respectively. Many features of the architecture are designed to be either pre-synthesis configurable or runtime programmable, which makes the processor extremely flexible, reusable, scalable, and practical.