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Yayın A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC(IEEE Computer Soc, 2008) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThis paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 390) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.Yayın A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264(IEEE, 2009) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinBit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing and etc. These attractive features make them suitable for using in VLSI design and reduce overall production cost. In this paper, we propose the first least significant bit (LSB) bit-serial sum of absolute difference (SAD) hardware accelerator for integer variable block size motion estimation (VBSME) of H.264. This hardware accelerator is based on a previous state-of-art bit-parallel architecture namely propagate partial SAD. In order to reduce area cost and improve throughput, pixel truncation technique is adopted. Due to the bit-serial pipeline architecture and using small processing elements, our architecture works at much higher clock frequency (at least 4 times) and reduces area cost about 32% compared with its bit-parallel counterpart. The proposed hardware accelerator can be used in different disciplines from low bit rate to high bit rate by making a tradeoff between the degree of parallelism or using fast algorithm or a combination of both.Yayın Retinal disease classification from bimodal OCT and OCTA using a CNN-ViT hybrid architecture(Institute of Electrical and Electronics Engineers Inc., 2025-09-21) Aydın, Ömer Faruk; Tek, Faik Boray; Turkan, YaseminRetinal diseases are the leading cause of vision impairment and blindness worldwide. Early and accurate diagnosis is critical for effective treatment, and recent advances in imaging technologies such as Optical Coherence Tomography (OCT) and OCT Angiography (OCTA), have enabled detailed visualization of the retinal structure and vasculature. By leveraging these modalities, this study proposes an advanced deep learning architecture called MultiModalNet for automated multi-class retinal disease classification. MultiModalNet employs a dual-branch design, where OCTA projection maps are processed through a ResNet101 encoder, and cross-sectional slices from the OCT volume (B-scans) are analyzed using a Vision Transformer (ViT-Large). The extracted features from both branches were fused and passed through the fully connected layers for the final classification. Evaluated on the 3-class OCTA-500 dataset, which includes Age-related Macular Degeneration (AMD), Diabetic Retinopathy (DR), and Normal cases, the proposed model achieved state-of-the-art classification accuracy of 94.59 percent, significantly o utperforming single-modality baselines. This result highlights the effectiveness of integrating vascular and structural information to improve the diagnostic performance. The findings suggest that hybrid multi-modal deep learning approaches can play a transformative role in computer-aided ophthalmology, enhancing both clinical decision-making and screening workflows.
