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Yayın QoS-constrained core selection for group communication(IEEE, 2005) Karaman, Ayşe; Hassanein, HossamThe core-based approach in multipoint communication enhances the solution space in terms of QoS-efficiency of solutions in inter and intra-domain routing. In an earlier work [KH04], we showed that the constrained cost minimization solutions in core-based approach proposed to date are restrictive in their search to a subrange of solutions, and we proposed SPAN, a generic framework to process in our identified extended solution space. In this paper, we study the core selection component of SPAN and propose two novel algorithms, SPAN/COST and SPAN/ADJUST, which define the core-selection component of SPAN. SPAN/COST mainly optimizes the cost distances to be traveled between the source-core and core-receiver pairs on the multicast trees, while SPAN/ADJUST selects the cores based on the numbers of nodes they dominate and adjusting the set based on cost. Our algorithms consistently outperform their counterparts proposed to date and can be considered pioneering in their optimization range of multiple metrics and processing in the extended solution space.Yayın Constraint-based routing in traffic engineering(IEEE, 2006) Karaman, AyşeTraffic engineering (TE) describes a domain-wide perspective for traffic control as opposed to application-specific concerns of QoS. MPLS is today's most powerful architecture for TE. Constraint-based routing refers to the process of path assignment to flows to fulfill the TE objective which has been defined in a number of multi-constraint ways, and is the most significant component of TE. In this paper, we review constraint-based routing algorithms. We first provide an overview of MPLS/TE and place constraint-based routing within this approach. We then look into the potential path attributes and the underlying platform to characterize these algorithms before we present our review. Our study provides a comprehensive reference to the operational structure and specifications of constraint-based routing algorithms.Yayın A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264(IEEE, 2009) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinBit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing and etc. These attractive features make them suitable for using in VLSI design and reduce overall production cost. In this paper, we propose the first least significant bit (LSB) bit-serial sum of absolute difference (SAD) hardware accelerator for integer variable block size motion estimation (VBSME) of H.264. This hardware accelerator is based on a previous state-of-art bit-parallel architecture namely propagate partial SAD. In order to reduce area cost and improve throughput, pixel truncation technique is adopted. Due to the bit-serial pipeline architecture and using small processing elements, our architecture works at much higher clock frequency (at least 4 times) and reduces area cost about 32% compared with its bit-parallel counterpart. The proposed hardware accelerator can be used in different disciplines from low bit rate to high bit rate by making a tradeoff between the degree of parallelism or using fast algorithm or a combination of both.
