Architecture of a fully pipelined real-time cellular neural network emulatort

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dc.authorid0000-0003-3988-0941
dc.authorid0000-0001-8590-1518
dc.authorid0000-0003-1382-9662
dc.contributor.authorYıldız, Nerhunen_US
dc.contributor.authorCesur, Evrenen_US
dc.contributor.authorKayaer, Kameren_US
dc.contributor.authorTavşanoğlu, Ahmet Vedaten_US
dc.contributor.authorAlpay, Murathanen_US
dc.date.accessioned2015-07-14T11:00:06Z
dc.date.available2015-07-14T11:00:06Z
dc.date.issued2015-01
dc.departmentIşık Üniversitesi, Mühendislik Fakültesi, Elektrik-Elektronik Mühendisliği Bölümüen_US
dc.departmentIşık University, Faculty of Engineering, Department of Electrical-Electronics Engineeringen_US
dc.description.abstractIn this paper, architecture of a Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v2) is given and the implementation results are discussed. The proposed architecture has a fully pipelined structure, capable of processing full-HD 1080p@60 (1920 1080 resolution at 60 Hz frame rate, 124.4 MHz visible pixel rate) video streams, which is implemented on both high-end and low-cost FPGA devices, Altera Stratix IV GX 230, and Cyclone III C 25, respectively. Many features of the architecture are designed to be either pre-synthesis configurable or runtime programmable, which makes the processor extremely flexible, reusable, scalable, and practical.en_US
dc.description.sponsorshipThis research was supported by The Scientific and Technological Research Council of Turkey (TUBITAK) under project number 108E023. This paper was recommended by Associate Editor M. Frascaen_US
dc.description.versionPublisher's Versionen_US
dc.identifier.citationYıldız, N., Cesur, E., Kayaer, K., Tavşanogğu, A. V. & Alpay, M. (2015). Architecture of a fully pipelined real-time cellular neural network emulator. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(1), 130-138. doi:10.1109/TCSI.2014.2345502en_US
dc.identifier.doi10.1109/TCSI.2014.2345502
dc.identifier.endpage138
dc.identifier.issn1549-8328
dc.identifier.issn1558-0806
dc.identifier.issue1
dc.identifier.scopus2-s2.0-85027947553
dc.identifier.scopusqualityQ1
dc.identifier.startpage130
dc.identifier.urihttps://hdl.handle.net/11729/584
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2014.2345502
dc.identifier.volume62
dc.identifier.wosWOS:000347706500014
dc.identifier.wosqualityQ1
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.indekslendigikaynakScience Citation Index Expanded (SCI-EXPANDED)en_US
dc.institutionauthorTavşanoğlu, Ahmet Vedaten_US
dc.institutionauthorid0000-0001-8590-1518
dc.language.isoenen_US
dc.peerreviewedYesen_US
dc.publicationstatusPublisheden_US
dc.publisherIEEE-INST Electrical Electronics Engineers Incen_US
dc.relation.ispartofIEEE Transactions on Circuits and Systems I: Regular Papersen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectCellular neural networksen_US
dc.subjectField programmable gate arraysen_US
dc.subjectReal time systemsen_US
dc.subjectReconfigurable architecturesen_US
dc.titleArchitecture of a fully pipelined real-time cellular neural network emulatorten_US
dc.typeArticleen_US
dspace.entity.typePublication

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