Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264
Yükleniyor...
Dosyalar
Tarih
2010-12
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
World Scientific Publishing Company
Erişim Hakkı
info:eu-repo/semantics/closedAccess
Özet
The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71-90.01% of area cost and improves the macroblock (MB) processing speed between 1.7-8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.
Açıklama
This work was supported in part by the Ministry of Higher Education, Malaysia, under Grant FRGS FP094/2007c. We would like to thank the reviewers of this paper for their helpful comments and suggestions which improved our paper. In addition, we would like to thank ARM and Silterra Malaysia for providing the standard cell libraries under the university program and Trans-Dist Engineering for its technical support.
Anahtar Kelimeler
Video compression, Sub-pixel motion estimation, H.264 standard, Bit-serial architecture, Vlsi architecture, Encoder, Reuse, Algorithms, Budget control, Computational complexity, Design, Estimation, Image compression, Optimization, Pixels, Standards, Video signal processing, Algorithm level, Area cost, Computational budget, Fast algorithms, Gate count, H.264 encoders, H.264 standards, Hardware architecture design, High resolution, High-speed operation, I/O pins, Low density, Low power application, Macro block, Memory access, Memory requirements, Operation frequency, Optimization techniques, Power consumption, Power savings, Processing speed, Proposed architectures, Quarter-pixel, Real time, Reference frame, Search method, Subpixel motion estimation, Sum of absolute differences, Video quality, Motion estimation
Kaynak
Journal of Circuits, Systems, and Computers
WoS Q Değeri
Q4
Scopus Q Değeri
Q3
Cilt
19
Sayı
8
Künye
Fatemi, M. R. H., Ateş, H. F. & Salleh, R. B. (2010). Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264. Journal of Circuits, Systems, and Computers, 19(8), 1665-1687. doi:10.1142/S0218126610006980
