An algorithm and its architecture for half-pixel variable block size motion estimation
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Dosyalar
Tarih
2007
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
IEEE
Erişim Hakkı
info:eu-repo/semantics/closedAccess
Özet
This paper presents an accurate half-pixel variable block size motion estimation algorithm and its hardware architecture. The proposed algorithm does not require interpolation of the reference frame pixels and has near performance to the conventional interpolation-search methods. These simplifications cause high level reduction in computational time and gate count without the need for internal or external half-pixel accuracy search memory. A simple, low latency, high throughput and fully utilized pipelined architecture of proposed algorithm is implemented in VHDL The proposed hardware architecture uses shift registers for multiplication and pipelining technique and can support half-pixel accuracy variable block size motion estimation for the real time HDTV format (1920 x1280 resolution and 30 Frames/sec).
Açıklama
Anahtar Kelimeler
AND gates, Automatic voltage control, Computational complexity, Computational time, Computer architecture, Copying, Delay, Diamond search, Digital television, Electron beam lithography, Estimation, External-, H.264, Half-pixel accuracy, Half-pixel variable block size motion estimation, Hardware, Hardware architecture, HDTV, High level computational reduction, High throughputs, Image coding, International conferences, Interpolation, ITS architecture, Low-latency, Malaysia, Motion estimation, Pipelined architecture, Pipelined architectures, Pixels, Real time, Real time HDTV format, Reference frames, Search memory, Search methods, Shift registers, Telecommunication systems, Television broadcasting, Throughput, Variable block size motion estimation, Vector quantization, Video coding, Video compression
Kaynak
2007 IEEE International Conference on Telecommunications and Malaysia International Conference on Communications
WoS Q Değeri
N/A
Scopus Q Değeri
N/A
Cilt
Sayı
Künye
Fatemi, M. R. H., Salleh, R. B. & Ateş, H. F. (2007). An algorithm and its architecture for half-pixel variable block size motion estimation. Paper presented at the 2007 IEEE International Conference on Telecommunications and Malaysia International Conference on Communications, 682-685. doi:10.1109/ICTMICC.2007.4448573
