A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264
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Dosyalar
Tarih
2009
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
IEEE
Erişim Hakkı
info:eu-repo/semantics/closedAccess
Özet
Bit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing and etc. These attractive features make them suitable for using in VLSI design and reduce overall production cost. In this paper, we propose the first least significant bit (LSB) bit-serial sum of absolute difference (SAD) hardware accelerator for integer variable block size motion estimation (VBSME) of H.264. This hardware accelerator is based on a previous state-of-art bit-parallel architecture namely propagate partial SAD. In order to reduce area cost and improve throughput, pixel truncation technique is adopted. Due to the bit-serial pipeline architecture and using small processing elements, our architecture works at much higher clock frequency (at least 4 times) and reduces area cost about 32% compared with its bit-parallel counterpart. The proposed hardware accelerator can be used in different disciplines from low bit rate to high bit rate by making a tradeoff between the degree of parallelism or using fast algorithm or a combination of both.
Açıklama
M This work was supported in part by the Ministry of Higher Education, Malaysia, under Grant FRGS FP094/2007c.
Anahtar Kelimeler
Architecture, Design, Area cost, Bit-parallel, Bit-serial, Bit-serial architecture, Clock frequency, Degree of parallelism, Fast algorithms, Hardware accelerators, High bit rates, Integer variables, Least significant bits, Low bit rate, Lower density, Pipeline architecture, Processing elements, Production cost, Sum of absolute differences, Truncation techniques, Variable block-size motion estimation, VLSI design, Cost reduction, Image coding, Industrial applications, Intelligent systems, Motion estimation, Vector quantization, Pipeline processing systems, Costs, Hardware, Clocks, Frequency, Bit rate, Pins, Routing, Very large scale integration, Production, Block codes, Code standards, Data compression, Parallel architectures, Video coding, VLSI, Least significant bit-serial architecture, Sum-of-absolute difference accelerator, H.264 standard, Bit-parallel architecture, Pixel truncation technique
Kaynak
2009 Innovative Technologies in Intelligent Systems and Industrial Applications
WoS Q Değeri
N/A
Scopus Q Değeri
N/A
Cilt
Sayı
Künye
Fatemi, M. R. H., Ateş, H. F. & Salleh, R. B. (2009). A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264. Paper presented at the 2009 Innovative Technologies in Intelligent Systems and Industrial Applications, 1-4. doi:10.1109/CITISIA.2009.5224251
