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Yayın An algorithm and its architecture for half-pixel variable block size motion estimation(IEEE, 2007) Fatemi, Mohammad Reza Hosseiny; Salleh, Rosli Bin; Ateş, Hasan FehmiThis paper presents an accurate half-pixel variable block size motion estimation algorithm and its hardware architecture. The proposed algorithm does not require interpolation of the reference frame pixels and has near performance to the conventional interpolation-search methods. These simplifications cause high level reduction in computational time and gate count without the need for internal or external half-pixel accuracy search memory. A simple, low latency, high throughput and fully utilized pipelined architecture of proposed algorithm is implemented in VHDL The proposed hardware architecture uses shift registers for multiplication and pipelining technique and can support half-pixel accuracy variable block size motion estimation for the real time HDTV format (1920 x1280 resolution and 30 Frames/sec).Yayın A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC(IEEE Computer Soc, 2008) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThis paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 390) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.Yayın A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264(IEEE, 2009) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinBit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing and etc. These attractive features make them suitable for using in VLSI design and reduce overall production cost. In this paper, we propose the first least significant bit (LSB) bit-serial sum of absolute difference (SAD) hardware accelerator for integer variable block size motion estimation (VBSME) of H.264. This hardware accelerator is based on a previous state-of-art bit-parallel architecture namely propagate partial SAD. In order to reduce area cost and improve throughput, pixel truncation technique is adopted. Due to the bit-serial pipeline architecture and using small processing elements, our architecture works at much higher clock frequency (at least 4 times) and reduces area cost about 32% compared with its bit-parallel counterpart. The proposed hardware accelerator can be used in different disciplines from low bit rate to high bit rate by making a tradeoff between the degree of parallelism or using fast algorithm or a combination of both.
