Arama Sonuçları

Listeleniyor 1 - 10 / 20
  • Yayın
    Teaching aliasing and spectral leakage through the sampling of images
    (Institute of Electrical and Electronics Engineers Inc., 2019-05-29) Tavşanoğlu, Ahmet Vedat
    Aliasing and spectral leakage are artifacts of sampling and rectangular windowing, respectively, whose manifestations are noticed in both the spatial and frequency domains. This paper aims to provide a classroom example which enables the recognition and mathematical interpretation of such phenomena.
  • Yayın
    New criteria for the existence of stable equilibrium points in nonsymmetric cellular neural networks
    (2003) Özcan, Neyir; Arık, Sabri; Tavşanoğlu, Ahmet Vedat
    This paper presents new criteria for the existence of stable equilibrium points in the total saturation region for cellular neural networks (CNNs). It is shown that the results obtained can be used to derive some complete stability conditions for some special classes of CNNs such as positive cell-linking CNNs, opposite-sign CNNs and dominant-template CNNs. Our results are also compared with the previous results derived in the literature for the existence of stable equilibrium points for CNNs.
  • Yayın
    Construction of the nodal conductance matrix of a planar resistive grid and derivation of the analytical expressions of its eigenvalues and eigenvectors using the Kronecker Product and Sum
    (IEEE, 2016-07-09) Tavşanoğlu, Ahmet Vedat
    This paper considers the task of constructing an (MxN+1)-node rectangular planar resistive grid as: first forming two (MxN+1)-node planar sub-grids; one made up of M of (N+1)-node horizontal, and the other of N of (M+1)-node vertical linear resistive grids, then joining their corresponding nodes. By doing so it is shown that the nodal conductance matrices GH and GV of the two sub-grids can be expressed as the Kronecker products GH = I-M circle times G(N), G(V) = G(M)circle times I-N, and G of the resultant planar grid as the Kronecker sum G = G(N circle plus) G(M), where G(M) and I-M are, respectively, the nodal conductance matrix of a linear resistive grid and the identity matrix, both of size M. Moreover, since the analytical expressions for the eigenvalues and eigenvectors of G(M) - which is a symmetric tridiagonal matrix- are well known, this approach enables the derivation of the analytical expressions of the eigenvalues and eigenvectors of G(H), G(V) and G in terms of those of G(M) and G(N), thereby drastically simplifying their computation and rendering the use of any matrix-inversion-based method unnecessary in the solution of nodal equations of very large grids.
  • Yayın
    A discussion on spatiotemporal filtering on a third generation real-time cellular neural network processor
    (IEEE Computer Society, 2016) Yıldız, Nerhun; Cesur, Evren; Tavşanoğlu, Ahmet Vedat
    A third generation Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v3) is a CNN emulator currently being implemented targeting FPGA devices. Thanks to the frame buffer support of the RTCNNP-v3 it will be possible to store and recall multiple frames which will extend the range of applications that can be implemented with RTCNNP, including spatiotemporal filters. In this paper, the implementation method of a velocity-tuned filter currently being implemented is disclosed with further discussion.
  • Yayın
    Sperm morphology analysis with CNN based algorithms
    (IEEE Computer Society, 2014-08-29) Şavkay, Osman Levent; Cesur, Evren; Yalçın, Müştak Erhan; Tavşanoğlu, Ahmet Vedat
    In this paper Morphological Analysis part of our proposed computer-aided sperm analysis system (CASA) is simulated and the results beside the algorithm steps are presented. The morphology analysis is simply dealing with shape of the sperms and extracting the shape characteristics in medical parameters. The characteristics are obtained by image processing algorithms which utilizes Cellular Nanoscale Network (CNN) based and spatial image processing blocks. The following calculation of medical parameters are obtained from the outputs of image processing blocks. The algorithm is so designed to adapt the final SoC architecture such as Xilinx Zynq7000 device.
  • Yayın
    New criteria for the existence of stable equilibrium points in nonsymmetric cellular neural networks
    (IEEE, 2003) Özcan, Neyir; Arık, Sabri; Tavşanoğlu, Ahmet Vedat
    A new criteria for the existence of stable equilibrium points in nonsymmetric cellular neural networks (CNN) was presented. It was shown that the results obtained can be used to derive some complete stability conditions for some special classes of CNNs such as positive cell-linking CNNs, opposite-sign CNNs and dominant-template CNNs. The model of the CNN whose dynamical behavior was described by the state equations was discussed.
  • Yayın
    Real-time frame buffer implementation based on external memory using FPGA
    (Elsevier B.V., 2018) Davutoğlu, Doğancan; Yıldız, Nerhun; Ayten, Umut Engin; Tavşanoğlu, Ahmet Vedat
    In this paper, design of a real-time video frame buffer with an external memory interface is proposed. In addition, simulation and implementation processes of the design is described. The mentioned system is able to buffer video signals up to 1920×1080 full-HD resolution at 60 Hz frame rate. The memory interface is designed based on an external SDRAM memory and supports burst read/write operations. Input video resolution, video buffer size on memory and burst size of the memory interface are user defined and can be configured.
  • Yayın
    Bir otomatik hedef tanıma algoritmasının geliştirilmesi
    (IEEE, 2013-04-24) Aldemir, Erdoğan; Yıldız, Nerhun; Tavşanoğlu, Ahmet Vedat
    Bu bildiri kapsamında bir Otomatik Hedef Tanıma (OHT) sistemi ele alınarak geliştirilmiş ve geliştirilen sistemin Matlab benzetimleri bildiride sunulmuştur. İkinci olarak OHT sistemlerinde kullanılan ve literatürde sıkça karşılaşılan klasik kenar belirleme algoritmalarının dışında yeni bir kenar belirleme algoritması önerilmiştir. Son olarak da Freeman zincir kodlamasının özellik çıkartma aşamasında kullanılabileceği gösterilmiştir. İlgili sistemin sınıflandırma ve karar verme aşaması hariç tamamı değişik test görüntüleri üzerinde denenmiş ve insan gözüne hitap edebilecek seviyede başarılı sonuçlar elde edilmiştir. İleride sınıflandırma aşamasının da gerçeklenmesi ile tasarlanan OHT sisteminin başarımının daha tarafsız bir ölçüt ile test edilmesi hedeflenmektedir. Ayrıca sistemin donanıma yönelik olarak optimizasyonu ile bir Field Programmable Gate Array (FPGA) gerçeklemesinin yapılması hedefler arasındadır.
  • Yayın
    Karma CPU + FPGA yapısı üzerinde tasarlanmış bilgisayar destekli sperm analizi sistemi
    (IEEE, 2015-06-19) Şavkay, Osman Levent; Tavşanoğlu, Ahmet Vedat; Yalçın, Müştak Erhan; Cesur, Evren
    Bu bildiride karma CPU + FPGA tabanlı bir donanım mimarisi üzerinde tasarlanan Bilgisayar Destekli Semen Analizi (BDSA) sistemi genel özellikleri ile anlatılmıştır. Spermatozoa motilite analizi hareketli çoklu nesne izleme algoritmasıdır, spermatozoa morfoloji analizi için ise ard arda uygulanan çeşitli durağan görüntü işleme yöntemleri ile yapılmaktadır. Sistemimizde kullanılan ve yüksek hız gerektiren hareketli ve durağan görüntü işleme işlevleri için FPGA yapısının paralel işlem yeteneğinden yararlanılmıştır. Çeşitli hesaplamalar ise geliştirilen özel yazılım ile CPU üzerinde gerçeklenmiştir. Biyolojik mikroskoba takılabilen bir HD dijital kamerayı da içermekte olan sistemimizin esnek programlanabilen ve tek başına çalışabilen bir akıllı sistem olarak çalışması da öngörülmüştür.
  • Yayın
    Realization of preprocessing blocks of CNN based CASA system on FPGA
    (2013) Şavkay, Osman Levent; Yıldız, Nerhun; Cesur, Evren; Yalçın Müştak, Erhan; Tavşanoğlu, Ahmet Vedat
    In this paper, hardware optimization of the preprocessing part of a computer aided semen analysis (CASA) system is proposed, which is also implemented on an FPGA device as a working prototype. A real-time cellular neural network (CNN) emulator (RTCNNP-v2) is used for the realization of the image processing algorithms, whose regular, flexible and reconfigurable infrastructure simplifies the prototyping process. For future work, the post-processing part of the CASA system is proposed to be implemented on the same FPGA device as software, using either a soft or hard processor core. By the integration of the pre- and post-processing parts, the designed CASA system will be capable of processing full-HD 1080p@60 (1080×1920) video images in real-time.