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Yayın Real-time video frame differentiator based on DDR3 SDRAM memory interface(IEEE Computer Society, 2018-08) Davutoğlu, Doğancan; Yıldız, Nerhun; Tavşanoğlu, Ahmet Vedat; Ayten, Umut EnginIn this paper, design of a real-time video frame differentiator based on an external memory interface is proposed. Furthermore, implementation and simulation processes of the design is discussed. The proposed design is capable of differentiating video frames over time, up to full-HD resolution at 60 Hz frame rate. An external SDRAM memory unit is used within the proposed design and drived by a memory interface. In order to improve the flexibility of the architecture, video resolution, video buffer size on memory and burst size of the memory interface are designed to be user defined and configurable.Yayın A discussion on spatiotemporal filtering on a third generation real-time cellular neural network processor(IEEE Computer Society, 2016) Yıldız, Nerhun; Cesur, Evren; Tavşanoğlu, Ahmet VedatA third generation Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v3) is a CNN emulator currently being implemented targeting FPGA devices. Thanks to the frame buffer support of the RTCNNP-v3 it will be possible to store and recall multiple frames which will extend the range of applications that can be implemented with RTCNNP, including spatiotemporal filters. In this paper, the implementation method of a velocity-tuned filter currently being implemented is disclosed with further discussion.Yayın Real-time frame buffer implementation based on external memory using FPGA(Elsevier B.V., 2018) Davutoğlu, Doğancan; Yıldız, Nerhun; Ayten, Umut Engin; Tavşanoğlu, Ahmet VedatIn this paper, design of a real-time video frame buffer with an external memory interface is proposed. In addition, simulation and implementation processes of the design is described. The mentioned system is able to buffer video signals up to 1920×1080 full-HD resolution at 60 Hz frame rate. The memory interface is designed based on an external SDRAM memory and supports burst read/write operations. Input video resolution, video buffer size on memory and burst size of the memory interface are user defined and can be configured.Yayın Bir otomatik hedef tanıma algoritmasının geliştirilmesi(IEEE, 2013-04-24) Aldemir, Erdoğan; Yıldız, Nerhun; Tavşanoğlu, Ahmet VedatBu bildiri kapsamında bir Otomatik Hedef Tanıma (OHT) sistemi ele alınarak geliştirilmiş ve geliştirilen sistemin Matlab benzetimleri bildiride sunulmuştur. İkinci olarak OHT sistemlerinde kullanılan ve literatürde sıkça karşılaşılan klasik kenar belirleme algoritmalarının dışında yeni bir kenar belirleme algoritması önerilmiştir. Son olarak da Freeman zincir kodlamasının özellik çıkartma aşamasında kullanılabileceği gösterilmiştir. İlgili sistemin sınıflandırma ve karar verme aşaması hariç tamamı değişik test görüntüleri üzerinde denenmiş ve insan gözüne hitap edebilecek seviyede başarılı sonuçlar elde edilmiştir. İleride sınıflandırma aşamasının da gerçeklenmesi ile tasarlanan OHT sisteminin başarımının daha tarafsız bir ölçüt ile test edilmesi hedeflenmektedir. Ayrıca sistemin donanıma yönelik olarak optimizasyonu ile bir Field Programmable Gate Array (FPGA) gerçeklemesinin yapılması hedefler arasındadır.Yayın Realization of preprocessing blocks of CNN based CASA system on FPGA(2013) Şavkay, Osman Levent; Yıldız, Nerhun; Cesur, Evren; Yalçın Müştak, Erhan; Tavşanoğlu, Ahmet VedatIn this paper, hardware optimization of the preprocessing part of a computer aided semen analysis (CASA) system is proposed, which is also implemented on an FPGA device as a working prototype. A real-time cellular neural network (CNN) emulator (RTCNNP-v2) is used for the realization of the image processing algorithms, whose regular, flexible and reconfigurable infrastructure simplifies the prototyping process. For future work, the post-processing part of the CASA system is proposed to be implemented on the same FPGA device as software, using either a soft or hard processor core. By the integration of the pre- and post-processing parts, the designed CASA system will be capable of processing full-HD 1080p@60 (1080×1920) video images in real-time.Yayın On the way to a third generation real-time cellular neural network processor(IEEE Computer Society, 2016) Yıldız, Nerhun; Cesur, Evren; Tavşanoğlu, Ahmet VedatIn this proceeding, the architecture of a third generation Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v3) is disclosed, which is a digital CNN emulator to be implemented on an FPGA device. The previous generation emulator, RTCNNP-v2, is the only CNN implementation reported to be capable of processing full-HD 1080p@60 (1080×1920 resolution at 60 Hz frame rate) video images in real-time. However, there are some weaknesses in both the design and implementation of RTCNNP-v2, like the inability to process different parts of the video images in parallel, lack of support for recording and recalling intermediate frames using external memory and it has some jitter issues at computation rates above 200 MHz. All of those issues are addressed in the next architecture of our CNN emulator, RTCNNP-v3, which is being implemented of an FPGA device.Yayın Design of a third generation real-time cellular neural network emulator(IEEE, 2014) Yıldız, Nerhun; Cesur, Evren; Tavşanoğlu, Ahmet VedatIn this paper, the features of the next generation Real-Time Cellular Neural Network Processor (RTCNNP-v3) are discussed. The RTCNNP-v2 structure is the only CNN implementation that is reported to be capable of processing full-HD 1080p@60 (1920 x 1080 resolution at 60 Hz frame rate) video images in real-time, due to its fully-pipelined architecture, however, it has some weaknesses like the inability to divide the processing in spatial domain, record and recall intermediate results to an external memory and has some issues in its internal memory coding. Those shortcomings are to be addressed in the next design of our CNN emulator - RTCNNP-v3, which will increase the range of applications and enable the implementation to match the requirements of the cutting-edge movie production technologies like UHD (4K) and the future FUHD (8K).Yayın Realization of processing blocks of CNN based CASA system on CPU and FPGA(IEEE, 2014) Şavkay, Osman Levent; Cesur, Evren; Yıldız, Nerhun; Yalçın, Mustak Erhan; Tavşanoğlu, Ahmet VedatIn this paper, hardware optimization of the preprocessing and software implementation of the processing blocks of a computer aided semen analysis (CASA) system are proposed, which is also implemented on an FPGA and ARM device as a working prototype. The software implementation of the track initialization, track maintenance, data validation and classification blocks of the processing part are implemented on a Zynq7000 ARM Cortex-A9 processor. In the preprocessing part, a real-time cellular neural network (CNN) emulator (RTCNNP-v2) is used for the realization of the image processing algorithms, whose regular, flexible and reconfigurable infrastructure simplifies the prototyping process. The CASA system introduced in this paper is capable of processing full-HD 1080p@60 (1080 x 1920) video images in real-time.Yayın Architecture of a fully pipelined real-time cellular neural network emulatort(IEEE-INST Electrical Electronics Engineers Inc, 2015-01) Yıldız, Nerhun; Cesur, Evren; Kayaer, Kamer; Tavşanoğlu, Ahmet Vedat; Alpay, MurathanIn this paper, architecture of a Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v2) is given and the implementation results are discussed. The proposed architecture has a fully pipelined structure, capable of processing full-HD 1080p@60 (1920 1080 resolution at 60 Hz frame rate, 124.4 MHz visible pixel rate) video streams, which is implemented on both high-end and low-cost FPGA devices, Altera Stratix IV GX 230, and Cyclone III C 25, respectively. Many features of the architecture are designed to be either pre-synthesis configurable or runtime programmable, which makes the processor extremely flexible, reusable, scalable, and practical.Yayın Demo: Real-time video frame differentiator based on external memory interface(IEEE Computer Society, 2018-08) Davutoğlu, Doğancan; Yıldız, Nerhun; Tavşanoğlu, Ahmet Vedat; Ayten, Umut EnginImplementation and demonstration processes of a real-time video frame differentiator based on an external memory interface is described in this paper. The video frame differentiation process is successfully implemented on both low cost and high-end FPGA development boards, then demonstrated by using sample videos at 1024x768@60 and 1920x1080@60 resolutions. Input video resolution, video buffer size on memory and burst size of the memory interface can be configured before implementation.
