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Yayın An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging(IEEE-INST Electrical Electronics Engineers Inc, 2009-10) Wygant, Ira O.; Jamal, Nafis S.; Lee, Hyunjoo J.; Nikoozadeh, Amin; Oralkan, Ömer; Karaman, Mustafa; Khuri-Yakub, Butrus ThomasState-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated property timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (B-scans) of a latex heart phantom.Yayın Detection of visual and frontoparietal network perfusion deficits in Parkinson's disease dementia(Elsevier Ireland Ltd, 2021-11) Azamat, Sena; Arslan, Dilek Betül; Erdoğdu, Emel; Kıçik, Ani; Cengiz, Sevim; Eryürek, Kardelen; Tüfekçioğlu, Zeynep; Bilgiç, Başar; Hanagasi, Haşmet; Demiralp, Tamer; Gürvit, Hakan; Öztürk Işık, EsinMild cognitive impairment of Parkinson's disease (PD) may be an early manifestation that may progressively worsen to dementia. Cognitive decline has been associated with changes in the brain perfusion pattern. This study aimed to evaluate cerebral blood flow (CBF) deficits specific to different stages of cognitive decline. Seventeen patients with cognitively normal PD (PD-CN), 18 patients with PD with mild cognitive impairment (PD-MCI), and 16 patients with PD with dementia (PDD) were included in this study. The participants were scanned using a 3 T Philips MRI scanner. Arterial spin labelling magnetic resonance (ASL-MR) images were acquired, followed by calculation of the CBF maps, and registration onto the MNI152 brain atlas. A whole-brain voxel-based CBF comparison was performed among the patient groups using age as a covariate. The mean age of patients with PDD was significantly higher than that of patients with PD-MCI (P = 0.015) and PD-CN (P = 0.001). The CBF values of the three groups were significantly different in the left cuneus of the visual network (VN), left inferior frontal gyrus of the frontoparietal network (FPN), and left dorsomedial nucleus of the thalamus. PDD had lower perfusion values than PD-MCI group in the same regions detected in the main group analysis. Additionally, comparison of PDD with PD-CN and non-demented groups revealed that the perfusion reduction extended into the bilateral cuneus of the VN, bilateral thalami, and left inferior frontal gyrus of the FPN. PDD could be separated from PD-MCI and PD-CN stages with CBF deficits in non-dopaminergically mediated posterior and dopaminergically mediated frontal networks.Yayın The routine design-modular distributed modeling platform for distributed routine design and simulation-based testing of distributed assemblies(Cambridge University Press, 2008-12-12) Eskil, Mustafa Taner; Sticklen, Jon; Radcliffe, ClarkIn this paper we describe a conceptual framework and implementation of a tool that supports task-directed, distributed routine design (RD) augmented with simulation-based design testing. In our research, we leverage the modular distributed modeling (MDM) methodology to simulate the interaction of design components in an assembly. The major improvement we have made in the RD methodology is to extend it with the capabilities of incorporating remotely represented off-the-shelf components in design and simulation-based testing of a distributed assembly. The deliverable of our research is the RD-MDM platform, which is capable of automatically selecting intellectually protected off the shelf design components over the Internet, integrating these components in an assembly, running simulations for design testing, and publishing the approved design without disclosing the proprietary information.Yayın A novel approach to the systematization of alpha-decaying nuclei, based on shell structures(Springer, 2016-05-24) Yarman, Nuh Tolga; Zaim, Nimet; Susam, Lidya Amon; Kholmetskii, Alexander; Arık, Metin; Altıntaş, Azmi Ali; Özaydın, FatihWe provide a novel systematization of alpha-decaying nuclei, starting with the classically adopted mechanism. The decay half-life of an alpha-disintegrating nucleus is framed, supposing that i) the alpha-particle is born inside the parent, then ii) it keeps on hitting the barrier, while it runs back and forth inside the parent, and hitting each time the barrier, and iii) it finally tunnels through the barrier. One can, knowing the decay half-life, consider the probability that the alpha-particle is born within the parent, before it is emitted, as a parameter. Under all circumstances, the decay appears to be governed by the shell structure of the given nucleus. Our approach well allows to incorporate (not only even-even nuclei, but) all nuclei, decaying via throwing an alpha particle. Though herein, we limit ourselves with just even-even nuclei, in the aim of comparing our results with the existing Geiger-Nuttal results.Yayın A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC(IEEE Computer Soc, 2008) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThis paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 390) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.Yayın A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264(IEEE, 2009) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinBit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing and etc. These attractive features make them suitable for using in VLSI design and reduce overall production cost. In this paper, we propose the first least significant bit (LSB) bit-serial sum of absolute difference (SAD) hardware accelerator for integer variable block size motion estimation (VBSME) of H.264. This hardware accelerator is based on a previous state-of-art bit-parallel architecture namely propagate partial SAD. In order to reduce area cost and improve throughput, pixel truncation technique is adopted. Due to the bit-serial pipeline architecture and using small processing elements, our architecture works at much higher clock frequency (at least 4 times) and reduces area cost about 32% compared with its bit-parallel counterpart. The proposed hardware accelerator can be used in different disciplines from low bit rate to high bit rate by making a tradeoff between the degree of parallelism or using fast algorithm or a combination of both.
