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Yayın Classification-based macroblock layer rate control for low delay transmission of H.263 video(IS & T - Soc Imaging Science Technology, 2003-07) Bayazıt, UluğPuri and Aravind's method of macroblock bit count estimation for video rate control is based on the classification of the macroblock data into discrete classes and assigning a unique non-linear estimate for each class and quantization parameter pair. This method stands apart from other methods in the literature, since the model of the bit count versus the quantization parameter relation, parameterized by macroblock variance, is a discrete model generated solely from measurements, We extend their technique for low-delay video rate control (tight buffer regulation) in two ways. We propose a strategy of near-uniform quantization parameter assignments to the macroblocks of a frame that can come close to maximizing an objective spatial quality function, such as PSNR, over the entire frame. We also adaptively update the quantization parameter assignments for the yet to be coded macroblocks, after the encoding of each macroblock, to compensate for any errors in the bit count estimation of the encoded macroblock. Our experiments demonstrate that the proposed rate control method can more accurately control the number of bits expended for a frame, as well as yield a higher objective spatial quality than the method adopted by TMN8.Yayın Crossing minimization in weighted bipartite graphs(Springer, 2007) Çakıroğlu, Olca Arda; Erten, Cesim; Karataş, Ömer; Sözdinler, MelihGiven a bipartite graph G = (L-0, L-1, E) and a fixed ordering of the nodes in L-0, the problem of finding an ordering of the nodes in L-1 that minimizes the number of crossings has received much attention in literature. The problem is NP-complete in general and several practically efficient heuristics and polynomial-time algorithms with a constant approximation ratio have been suggested. We generalize the problem and consider the version where the edges have nonnegative weights. Although this problem is more general and finds specific applications in automatic graph layout problems similar to those of the unweighted case, it has not received as much attention. We provide a new technique that efficiently approximates a solution to this more general problem within a constant approximation ratio of 3. In addition we provide appropriate generalizations of some common heuristics usually employed for the unweighted case and compare their performances.Yayın Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264(World Scientific Publishing Company, 2010-12) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThe sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71-90.01% of area cost and improves the macroblock (MB) processing speed between 1.7-8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.
