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Yayın A survey of algorithms and architectures for H.264 sub-pixel motion estimation(World Scientific, 2012-05) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThis paper reviews recent state-of-the-art H. 264 sub-pixel motion estimation (SME) algorithms and architectures. First, H.264 SME is analyzed and the impact of its functionalities on coding performance is investigated. Then, design space of SME algorithms is explored representing design problems, approaches, and recent advanced algorithms. Besides, design challenges and strategies of SME hardware architectures are discussed and promising architectures are surveyed. Further perspectives and future prospects are also presented to highlight emerging trends and outlook of SME designs.Yayın An algorithm and its architecture for half-pixel variable block size motion estimation(IEEE, 2007) Fatemi, Mohammad Reza Hosseiny; Salleh, Rosli Bin; Ateş, Hasan FehmiThis paper presents an accurate half-pixel variable block size motion estimation algorithm and its hardware architecture. The proposed algorithm does not require interpolation of the reference frame pixels and has near performance to the conventional interpolation-search methods. These simplifications cause high level reduction in computational time and gate count without the need for internal or external half-pixel accuracy search memory. A simple, low latency, high throughput and fully utilized pipelined architecture of proposed algorithm is implemented in VHDL The proposed hardware architecture uses shift registers for multiplication and pipelining technique and can support half-pixel accuracy variable block size motion estimation for the real time HDTV format (1920 x1280 resolution and 30 Frames/sec).Yayın A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC(IEEE Computer Soc, 2008) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThis paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 390) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.Yayın Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264(World Scientific Publishing Company, 2010-12) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThe sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71-90.01% of area cost and improves the macroblock (MB) processing speed between 1.7-8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.
