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Yayın Çok-hipotezli süperpikseller ile sahne bölütleme ve etiketleme(IEEE, 2015-06-19) Ak, Kenan Emir; Ateş, Hasan FehmiSüperpikseller son zamanlarda imge bölütleme ve sınıflandırma problemlerinde giderek önem kazanmaktadır. Sahne etiketlemede imge öncelikle bir süperpiksel algoritması ile görsel olarak tutarlı küçük parçalara bölütlenmekte; daha sonra süperpikseller farklı sınıflara ayrı¸stırılmaktadır. Sınıflandırma performansı kullanılan süperpiksel algoritmasının özellikleri ve parametre ayarlarından önemli ölçüde etkilenmektedir. Bu bildiride sahne etiketleme doğruluğunu iyileştirmek için birden fazla süperpiksel bölütleme sonucunu sınıflandırıcı seviyesinde kaynaştıran bir yöntem önerilmiştir. Öncelikle basit, parametrik olmayan ve eğitim gerektirmeyen SuperParsing algoritması kullanılarak süperpiksel etiketleri için olabilirlik oranları tespit edilir. Daha sonra alternatif süperpiksel bölütleme senaryoları için hesaplanan olabilirlik oranları piksel seviyesinde kaynaştırılarak, ilgili sahnenin bölütlenmesi ve etiketlenmesi tamamlanır. Önerilen yöntem 2,688 imge ve 33 etiket içeren SIFT Flow veri kümesi üzerinde test edilmiş ve SuperParsing’den daha yüksek sınıflandırma doğruluğu elde edilmiştir.Yayın Kernel kod-tablosu kodlaması ile sahne etiketleme(IEEE, 2017-06-27) Ateş, Hasan Fehmi; Sünetci, SercanSahne bölütleme ve etiketlemede son yıllarda süperpiksel tabanlı yaklaşımların başarılı olduğu görülmektedir. Öncelikle görüntü bir süperpiksel algoritması ile görsel olarak tutarlı küçük parçalara bölütlenmekte; daha sonra her süperpiksel için çeşitli öznitelik betimleyicileri hesaplanıp sınıflandırma yapılmaktadır. Bu bildiride süperpiksel öznitelikleri için Kernel Kodtablosu Kodlama (KKT) yaklaşımı önerilmiştir. KKT’de öznitelik vektörleri için sabit nicemleme yerine birden fazla kodsözcüğüne yumuşak eşlemleme yapılmaktadır. Kodsözcüklerine atanan ağırlıklar bir kernel uzaklık fonksiyonu ile hesaplanmaktadır. KKT yöntemi SuperParsing görüntü ayrıştırma algoritmasında SIFT özniteliklerinin kodlanması için kullanılmıştır. Geliştirdiğimiz yöntem 2,688 görüntü ve 33 sınıf içeren SIFT Flow veri kümesi kullanılarak denenmiş ve SuperParsing yönteminden %2.7 daha yüksek ayrıştırma doğruluğu sağlanmıştır.Yayın Kernel likelihood estimation for superpixel image parsing(Springer Verlag, 2016) Ateş, Hasan Fehmi; Sünetci, Sercan; Ak, Kenan EmirIn superpixel-based image parsing, the image is first segmented into visually consistent small regions, i.e. superpixels; then superpixels are parsed into different categories. SuperParsing algorithm provides an elegant nonparametric solution to this problem without any need for classifier training. Superpixels are labeled based on the likelihood ratios that are computed from class conditional density estimates of feature vectors. In this paper, local kernel density estimation is proposed to improve the estimation of likelihood ratios and hence the labeling accuracy. By optimizing kernel bandwidths for each feature vector, feature densities are better estimated especially when the set of training samples is sparse. The proposed method is tested on the SIFT Flow dataset consisting of 2,688 images and 33 labels, and is shown to outperform SuperParsing and some of its extended versions in terms of classification accuracy.Yayın An algorithm and its architecture for half-pixel variable block size motion estimation(IEEE, 2007) Fatemi, Mohammad Reza Hosseiny; Salleh, Rosli Bin; Ateş, Hasan FehmiThis paper presents an accurate half-pixel variable block size motion estimation algorithm and its hardware architecture. The proposed algorithm does not require interpolation of the reference frame pixels and has near performance to the conventional interpolation-search methods. These simplifications cause high level reduction in computational time and gate count without the need for internal or external half-pixel accuracy search memory. A simple, low latency, high throughput and fully utilized pipelined architecture of proposed algorithm is implemented in VHDL The proposed hardware architecture uses shift registers for multiplication and pipelining technique and can support half-pixel accuracy variable block size motion estimation for the real time HDTV format (1920 x1280 resolution and 30 Frames/sec).Yayın A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC(IEEE Computer Soc, 2008) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThis paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 390) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.Yayın Analysis and design of low-cost bit-serial architectures for motion estimation in H.264/AVC(Springer, 2013-05) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinVariable block-size motion estimation (VBSME) process occupies a major part of computation of an H.264 encoder, which is usually accelerated by bit-parallel hardware architectures with large I/O bit width to meet real-time constrains. However, such kind of architectures increase the area overhead and pin count, and therefore will not be suitable for area-constrained electronic consumer designs such as small portable multimedia devices. This paper addresses this problem by proposing two area efficient least significant bit (LSB) bit-serial architectures with small pin numbers. Both designs take advantage of data reusing technique in different ways for sum of absolute differences (SAD) computation and reading reference pixels, leading to a considerable reduction of memory bandwidth. The first architecture propagates the partial SAD and sum results and broadcasts the reference pixel rows whereas the second design reuse the SAD of small blocks and has a reconfigurable reference buffer leading to a better memory bandwidth when using hardware parallelism. The proposed designs benefit from several optimization techniques including an efficient serial absolute difference architecture, word length reduction by parallelism, bit truncation, mode filtering, and macroblock (MB) level subsampling, which significantly enhance their performances in terms of silicon area, throughput, latency, and power consumption. The first and second designs can support full search VBSME of 720 x 480 video with 30 frames per second (fps), two reference frames, and [-16, 15] search range at a clock frequency of 414 MHz with 29.28 k and 31.5 k gates, respectively.Yayın Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264(World Scientific Publishing Company, 2010-12) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThe sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71-90.01% of area cost and improves the macroblock (MB) processing speed between 1.7-8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.
